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1 of 17 021604 special features 4096 bits of read/write nonvolatile memory (ds1993) 1024 bits of read/write nonvolatile memory (DS1992) 256-bit scratchpad ensure s integrity of data transfer memory partitioned in to 256-bit pages for packetizing data data integrity assured with strict read/write protocols operating temperature range from -40c to +70c over 10 years of data retention common ibutton features unique, factory-lasered and tested 64-bit registration number (8-bit family code + 48-bit serial number + 8-bit crc tester) assures absolute traceability because no two parts are alike multidrop controller for microlan digital identification and information by momentary contact chip-based data carrier compactly stores information data can be accesse d while affixed to object economically communicates to bus master with a single digital signal at 16.3kbps standard 16mm diameter and 1-wire ? protocol ensure compatibility with ibutton ? family button shape is self-aligning with cup- shaped probes durable stainless steel case engraved with registration number withstands harsh environments easily affixed with self-stick adhesive backing, latched by its flange, or locked with a ring pressed onto its rim presence detector acknowledges when reader first applies voltage meets ul#913 (4th edit.); intrinsically safe apparatus, approved under entity concept for use in class i, division 1, group a, b, c and d locations f5 microcan io gnd 0.36 0.51 5.89 ? 1993 yyww registered rr dd 06 000000fbd804 16.25 17.35 all dimensions shown in millimeters. ordering information DS1992l-f5 f5 microcan ds1993l-f5 f5 microcan examples of accessories ds9096p self-stick adhesive pad ds9101 multipurpose clip ds9093ra mounting lock ring ds9093f snap-in fob ds9092 ibutton probe DS1992/ds1993 1kb/4kb memory ibutton www.ibutton.com 1-wire and ibutton are registered trademarks of dallas semiconductor.
DS1992/ds1993 2of 2 ibutton description the DS1992/ds1993 memory ibuttons (hereafter referred to as ds199_) are rugged read/write data carriers that act as a localized database, eas ily accessible with minimal hardware. the nonvolatile memory and optional timekeeping capability offer a simple solution to storing and retrieving vital information pertaining to the object to which the ibu tton is attached. data is transferred serially through the 1-wire protocol that requires only a single data lead and a ground return. the scratchpad is an additional page that acts as a buffer when writing to memory. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command transfers the data to memory. this process ensures data integrity when modifying the memory. a 48-bit serial number is factory lasered into each ds199_ to provide a guaranteed unique identity that allows for absolute traceability. the durable microcan package is highly resistant to environmental hazards such as dirt, moisture, and shock. its compact coin-shaped profile is self-aligning with mating receptacles, allowing the ds199_ to be easily used by human operators. accessories permit the ds199_ to be mounted on almost any surface including plas tic key fobs, photo?id badges, and pc boards. applications include access control, work-in-progress tracking, electroni c travelers, storage of calibration constants, and debit tokens. operation the ds199_ have three main data components: 1) 64-bit lasered rom, 2) 256-bit scratchpad, and 3) 1024-bit (DS1992) or 4096-bit (ds1993) sram. all data is read and wr itten least significant bit first. the memory functions are not available until the rom function protocol has been established. this protocol is described in the rom functions flow ch art (figure 9). the master must first provide one of four rom function commands: 1) read rom, 2) match rom, 3) search rom, or 4) skip rom. after a rom function sequence has been successfully execu ted, the memory functions are accessible and the master can then provide any one of the four memory function commands (figure 6). parasite power the block diagram (figure 1) shows the parasite-power ed circuitry. this circuitry steals power whenever the data input is high. the data line provides suffic ient power as long as the specified timing and voltage requirements are met. the advantages of parasite power are two-fold: 1) by parasiting off this input, lithium is conserved, and 2) if the lithium is exhausted for any reason, the rom can still be read normally. 64-bit lasered rom each ds199_ contain a unique rom code that is 64 bits long. the first 8 bits are a 1-wire family code. the next 48 bits are a unique serial number. the last 8 bits are a crc of the first 56 bits. (see figure 2.) the 1-wire crc is generated using a polynomial generator consisting of a shift register and xor gates as shown in figure 3. the polynomial is x 8 + x 5 + x 4 + 1. additional informati on about the dallas 1-wire cyclic redundancy check is available in the book of ds19xx ibutton standards. the shift register bits are initialized to zero. then starting with the least significant bit of the family code, 1 bit at a time is shifted in. after the 8th bit of the family code has been entered, then the serial number is entered. after the 48th bit of the serial number has been entered, the shift register contains the crc value. shifting in the 8 bits of crc should return the shift register to all zeros.
DS1992/ds1993 3of 3 figure 1. ds199_ block diagram sram 16 pages of 256- bits (1993) 256-bit scratchpad 1-w rom control function 64-bit rom lasered parasite- circuitry powered memory function control 1-wire port 3v lithium 4 pages of 256- bits (1992) figure 2. 64-bit lasered rom msb lsb 8-bit crc code 48-bit serial number 8-bit family code (06h)1993 (08h)1992 msb lsb msb lsb msb lsb figure 3. 1-wire crc code x 0 x 1 x 2 x 3 x 4 x 5 x 6 x 7 x 8 polynomial = x 8 + x 5 + x 4 + 1 1 st stage 2 nd stage 3 rd stage 4 th stage 6 th stage 5 th stage 7 th stage 8 th stage input data
DS1992/ds1993 4of 4 figure 4a. ds1993 memory map page 0 page page 1 page 2 page 3 page 4 page 5 page 6 page 7 page 8 page 9 page 10 page 11 page 12 page 13 page 14 page 15 scratchpad memory 0000h 0020h 0040h 0060h 0080h 00a0h 00c0h 00e0h 0100h 0120h 0140h 0160h 0180h 01a0h 01c0h 01e0h note: each page is 32 bytes (256 bits). the hex values represent the starting address for each page or register. figure 4b. DS1992 memory map page 0 page page 1 page 2 page 3 scratchpad memory 0000h 0020h 0040h 0060h note: each page is 32 bytes (256 bits). the hex values represent the starting address for each page or register.
DS1992/ds1993 5of 5 memory the memory map in figure 4 shows a 32-byte page called the scratchpad, and additional 32-byte pages called memory. the DS1992 contains pages 0 t hough 3 that make up the 1024-bit sram. the ds1993 contain pages 0 through 15 that make up the 4096-bit sram. the scratchpad is an additional page that acts as a buffer when writing to memory. data is first written to the scratchpad where it can be read back. after the data has been verified, a copy scratchpad command transfers the data to memory. this process ensures data integrity when modifying the memory. memory function commands the memory function flow chart (figure 6) describe s the protocols necessary for accessing the memory. an example follows the flow chart. three address registers are provided as shown in figure 5. the first two registers represent a 16-bit targ et address (ta1, ta2). the third re gister is the ending offset/data status byte (e/s). the target address points to a unique byte location in memory. the first 5 bits of the target address (t4:t0) represent the byte offset within a page. this byte offset points to one of 32 possible byte locations within a given page. for instance, 00000b poi nts to the first byte of a page where as 11111b would point to the last byte of a page. the third register (e/s) is a read only register. the first 5 bits (e4: e0) of this register are called the ending offset. the ending offset is a byte offset within a page (1 of 32 bytes). bit 5 (pf) is the partial byte flag. bit 6 (of) is the overflow flag. bit 7 (aa) is the authorization accepted flag. figure 5. address registers 76543210 target address (ta1) t7 t6 t5 t4 t3 t2 t1 t0 target address (ta2) t15 t14 t13 t12 t11 t10 t9 t8 ending address with data status (e/s) (read only) aa of pf e4 e3 e2 e1 e0 write scratchpad command [0fh] after issuing the write scratchpad command, the user must first provide the 2-byte target address, followed by the data to be written to the scratchpad. the data is written to the scratchpad starting at the byte offset (t4:t0). the ending offset (e4:e0) is the byte offset at which the host stops writing data. the maximum ending offset is 11111b (31d). if the host attempts to write data past this maximum offset, the overflow flag (of) is set and the remaining data is ignored. if the user writes an incomplete byte and an overflow has not occurred, the pa rtial byte flag (pf) is set. read scratchpad command [aah] this command can be used to verify scratchpad data and targ et address. after issuing the read scratchpad command, the user can begin reading. the first two byte s are the target address. the next byte is the ending offset/data status byte (e/s) followed by the sc ratchpad data beginning at the byte offset (t4: t0). the user can read data until the end of the scratc hpad, after which the data read is all logic 1?s.
DS1992/ds1993 6of 6 copy scratchpad [55h] this command is used to copy data from the scratchpad to memory. after issuing the copy scratchpad command, the user must provide a 3-by te authorization pattern. this pa ttern must exactly match the data contained in the three address registers (ta1, ta2, e/ s, in that order). if the pattern matches, the aa (authorization accepted) flag is set and the copy be gins. a logic 0 is transmitted after the data has been copied until the user issues a reset pulse. any attempt to reset the part is ignored while the copy is in progress. copy typically takes 30 s. the data to be copied is determined by the three address registers. the scratchpad data from the beginning offset through the ending offset is copied to memory, starting at the target address. anywhere from 1 to 32 bytes can be copied to memory with this command. whole bytes are copied even if only partially written. the aa flag is cleared only by executing a write scratchpad command. read memory [f0h] the read memory command can be used to read the entire memory. after issuing the command, the user must provide the 2-byte target address. after the two bytes, the user reads data beginning from the target address and may continue until the end of memory, at which point logic 1?s are read. it is important to realize that the target address registers contains th e address provided. the ending offset/data status byte is unaffected. the hardware of the DS1992/ds1993 provides a means to accomplish error-free writing to the memory section. to safeguard reading data in the 1-wire environment and to s imultaneously speed up data transfers, it is recommended to packetize data into data packets of the size of one memory page each. such a packet would typically store a 16-bit crc with each page of data to ensure rapid, error-free data transfers that eliminate having to read a page multiple times to determine if the received data is correct or not. (see application note 114 for the recommended file structure to be used with the 1-wire environment.)
DS1992/ds1993 7of 7 figure 6. memory functions flow chart master tx memory function command y ds199x sets scratchpad offset = (t4:t0) and clears (pf, of, aa) ds199x sets (e4:e0) = scratchpad offset ds199x increments scratchpad offset bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) master tx data byte to scratchpad offset bus master tx reset ? n 0fh write ? scratchpad n bus master tx data ? y n pf = 1 n y bus master tx reset ? to figure 6 second part bus master rx ta1 (t7:t0) bus master rx ta2 (t15:t8) master rx ending offset with data status (e/s) ds199x sets scratchpad offset=(t4:t0) bus master tx reset ? ds199x increments scratchpad offset y master rx data byte from scratchpad offset n n scratch- pad offset = 11111b ? y y scratchpad aah read ? bus master rx "1"s from figure 6 second part of = 1 scratch- pad offset = 11111b ? n partial byte written ? n y y y ds199x tx presence pulse (see figure 9)
DS1992/ds1993 8of 8 figure 6. memory functions flow chart (continued) y n bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) scratchpad 55h copy ? n y from figure 6 first part bus master tx e/s byte ds199x copies scratchpad data to memory auth- code match ? ds199x tx "1"s ds199x tx "0"s aa = 1 f0h read memory ? n to figure 6 first part y n bus master tx reset ? bus master tx reset ? y n y y bus master tx ta1 (t7:t0) bus master tx ta2 (t15:t8) ds199x sets memory address = (t15:t0) n y n master rx data byte from memory address bus master tx reset ? memory ds199x address counter increments bus master rx "1"s address = 21dh ? rization
DS1992/ds1993 9of 9 memory function examples example: write two data bytes to memory locations 0026h and 0027h (t he seventh and eighth bytes of page 1). read entire memory. master mode data (lsb first) comments tx reset reset pulse (480 s to 960 s) rx presence presence pulse tx cch issue skip rom command tx 0fh issue write scratchpad command tx 26h ta1, beginning offset = 6 tx 00h ta2, address = 0026h tx <2 data bytes> write 2 by tes of data to scratchpad tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx aah issue read scratchpad command rx 26h read ta1, beginning offset = 6 rx 00h read ta2, address = 0026h rx 07h read e/s, ending offset = 7, flags = 0 rx <2 data bytes> read sc ratchpad data and verify tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx 55h issue copy scratchpad command tx 26h tx 00h tx 07h ta1 ta2 authorization code e/s tx reset reset pulse rx presence presence pulse tx cch issue skip rom command tx f0h issue read memory command tx 00h ta1, beginning offset = 6 tx 00h ta2, address = 0000h rx <128 bytes (DS1992)> <512 bytes (ds1993)> read entire memory tx reset reset pulse rx presence presence pulse, done
DS1992/ds1993 10of 10 1-wire bus system the 1-wire bus is a system that has a single bus master and one or more slaves. in all instances the ds199_ is a slave device. the bus ma ster is typically a microcontrolle r or pc. for small configurations the 1-wire communication signals can be generated under software cont rol using a single port pin. for multisensor networks, the ds2480b 1-wire line driver chip or serial port adapters based on this chip (ds9097u series) are recommended. th is simplifies the hardware desi gn and frees the microprocessor from responding in real-time. the discussion of this bus system is broken down into three topics: hardware configuration, transaction sequence, and 1-wire signaling (signal types and timing). the 1-wire protocol defines bus transactions in terms of the bus state during specific time slots that are initiated on the falling edge of sync pulses from the bus master. for a more detailed protocol description, refer to chapter 4 of the book of ds19xx ibutton standards . hardware configuration the 1-wire bus has only a single line by definition; it is important that each device on the bus be able to drive it at the appropriate time. to facilitate this, each device attached to the 1-wire bus must have open- drain or three-state outputs. the 1-wire port of the ds199_ is open drain with an internal circuit equivalent to that shown in figure 8. a multidrop bus consists of a 1-wire bus with multiple slaves attached. the 1-wire bus has a maximum data rate of 16.3kbps and require s a pullup resistor of approximately 5k . the idle state for the 1-wire bus is hig h. if for any reason a transaction needs to be suspended, the bus must be left in the idle state if the transaction is to resume. if this does not occur and the bus is left low for more than 120 s, one or more of the devices on the bus may be reset. figure 8. hardware configuration open drain port pin rx = receive tx = transmit 100 mosfet v pup rx tx tx rx data r pu 5 a typ. bus master ds199x 1-wire port transaction sequence the protocol for accessing the ds199_ thro ugh the 1-wire port is as follows: initialization rom function command memory function command transaction/data initialization all transactions on the 1-wire bus begin with an initialization sequence. the initialization sequence consists of a reset pulse transmitted by the bus master followed by presence pulse(s) transmitted by the
DS1992/ds1993 11of 11 slave(s). the presence pulse lets the bus master know that the ds199_ is on the bus and is ready to operate. for more details, see the 1-wire signaling section. rom function commands once the bus master has detected a presence, it ca n issue one of the four rom function commands. all rom function commands are 8 bits long. a list of these commands follows (see the flow chart in figure 9). read rom [33h] this command allows the bus master to read the ds199_?s 8-bit family code, unique 48-bit serial number, and 8-bit crc. this command should only be used if there is a single ds199_ on the bus. if more than one slave is present on the bus, a data collision occurs when all slaves try to transmit at the same time (open drain produces a wi red-and result). the resultant famil y code and 48-bit serial number usually result in a mismatch of the crc. match rom [55h] the match rom command, followed by a 64-bit rom se quence, allows the bus master to address a specific ds199_ on a multidrop bus. only the ds199_ th at exactly matches the 64-bit rom sequence will respond to the following memory function comma nd. all slaves that do not match the 64-bit rom sequence wait for a reset pulse. this command can be used with single or multiple devices on the bus. skip rom [cch] this command can save time in a single drop bus system by allowing the bus master to access the memory functions without providing the 64-bit rom code. if more than one slave is present on the bus and, for example, a read command is issued followi ng the skip rom command, data collision will occur on the bus as multiple slaves transmit simultane ously (open-drain pulldowns produce a wired-and result). search rom [f0h] when a system is initially brought up, the bus mast er may not know the number of devices on the 1-wire bus or their 64-bit rom codes. the search rom co mmand allows the bus master to use a process of elimination to identify the 64-bit rom codes of all slave devices on the bus. the search rom process is the repetition of a simple 3-step routine: read a bit, read the complement of the bit, then write the desired value of that bit. the bus master performs this simple, 3-step routine on each bit of the rom. after one complete pass, the bus master knows the 64-bit rom code of one device. additional passes will identify the rom codes of the remaining de vices. see chapter 5 of the book of ds19xx ibutton standards for a comprehensive discussion of a search rom, including an actual example. 1-wire signaling the ds199_ require strict protocols to ensure data integrity. the prot ocol consists of four types of signaling on one line: reset sequence with reset pulse and presence pulse, write 0, write 1, and read data. the bus master initiates all these signals except presence pulse. the initialization sequence required to begin any communication with the ds199_ is shown in figure 10. a reset pulse followed by a presence pulse indicates the ds199_ is ready to send or receive data given the correct rom command and memory function command. the bus master transmits (tx) a reset pulse (t rstl , minimum 480 s). the bus master then releases the line and goes into receive mode (rx). the 1-wire bus is pulled to a high state through the pullup resistor. after detecting the rising edge on the data line, the ds199_ waits (t pdh , 15 s to 60 s) and then transmits the presence pulse (t pdl , 60 s to 240 s).
DS1992/ds1993 12of 12
DS1992/ds1993 13of 13 figure 9. rom functions flow chart f0h search rom command ? cch skip rom command ? ds199x tx bit 0 ds199x tx bit 0 master tx bit 0 bit 0 match ? ds199x tx bit 1 ds199x tx bit 1 master tx bit 1 bit 1 match ? ds199x tx bit 63 ds199x tx bit 63 master tx bit 63 bit 63 match ? master tx memory function command 33h read rom command ? ds199x tx serial number 6 bytes ds199x tx crc byte ds199x tx family code 1 byte match rom 55h command ? bit 0 match ? bit 1 match ? bit 63 match ? master tx bit 1 master tx bit 0 n y n y nn y n n n n y y y y y y n y n master tx rom function command master tx reset pulse ds199x tx presence pulse master tx bit 63
DS1992/ds1993 14of 14 figure 10. initialization procedure reset and presence pulse resistor master ds199x master rx "presence pulse" 480 s t rstl < * 480 s t rsth < ** 15 s t pdh < 60 s 60 t pdl < 240 s master tx "reset pulse" v pullup v pullup min v ih min v il max 0v t rsth t rstl t pdh t pdl t r * in order not to mask interrup signaling by other devices on the 10wire bus t rstl + t r should always be less than 960 us ** includes recovery time read/write time slots the definitions of write and read time slots are illustrated in figure 11. the master driving the data line low initiates all time slots. the fa lling edge of the data line synchronizes the ds199_ to the master by triggering a delay circuit in the ds199_. during write time slots, the delay circuit determines when the ds199_ samples the data line. for a read data time sl ot, if a 0 is to be transmitted, the delay circuit determines how long the ds199_ holds the data line low overriding the 1 generated by the master. if the data bit is a 1, the ibutton leaves the read data time slot unchanged. figure 11. read/write timing diagram write-one time slot 15s 60s ds199x sampling window v pullup v pullup min v ih min v il max 0v t slot t rec t low1 60 s t slot < 120 s 1 s t low1 < 15 s 1 s t rec < resistor master
DS1992/ds1993 15of 15 figure 11. read/write timing diagram (continued) write-zero time slot 15s resistor master ds199x 60s t low0 sampling window 60 s t low0 < t slot < 120 s 1 s t rec < v pullup v pullup min v ih min v il max 0v t slot t rec read-data time slot resistor master ds199x master sampling window 60 s t slot < 120 s 1 s t lowr < 15 s 0 t release < 45 s 1 s t rec < t rdv = 15 s t su < 1 s v pullup v pullup min v ih min v il max 0v t slot t rec t lowr t su t rdv t release
DS1992/ds1993 16of 16 physical specifications size see mechanical drawing weight 3.3 grams (f5 package) expected service life 10 years at +25 c safety meets ul#913 (4th edit.); intrinsically safe apparatus, approved under entity concept for use in class i, division 1, group a, b, c and d locations absolute maximum ratings* voltage on any pin relativ e to ground -0.5v to +7.0v operating temperature range -40 c to +70 c storage temperature range -40 c to +70 c * this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operation sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods of time may affect reliability. dc electrical characteristics (v pup = 2.8v to 6.0v; -40c to +70c.) parameter symbol min typ max units logic 1 (notes 1, 2) v ih 2.2 v logic 0 (note 1) v il -0.3 +0.8 v output logic low at 4ma (note 1) v ol 0.4 v output logic high (notes 1, 3) v oh v pup v input load current (note 4) i l 5 a capacitance (t a = +25c) parameter symbol min typ max units i/o (1-wire) (notes 5, 6) c in/out 100 800 pf ac electrical characteristics (v pup = 2.8v to 6.0v; -40c to +70c.) parameter symbol min typ max units time slot t slot 60 120 s write 1 low time t low1 115 s write 0 low time t low0 60 120 s read data valid t rdv exactly 15 s release time t release 015 45 s read data setup (note 7) t su 1 s recovery time t rec 1 s reset time high (note 8) t rsth 480 s reset time low (note 9) t rstl 480 960 s presence detect high t pdh 15 60 s presence detect low t pdl 60 240 s
DS1992/ds1993 17of 17 note 1: all voltages are referenced to ground. note 2: v ih is a function of the external pullup resistor and the v cc power supply. note 3: v pup = external pullup voltage. note 4: input load is to ground. note 5: capacitance on the data line could be 800p f when power is first applied. if a 5k resistor is used to pull up the data line to v pup , 5 s after power has been applie d, the parasite capacitance does not affect normal communications. note 6: guaranteed by design, not production tested. note 7: read data setup time refers to the time the host must pull the 1-wire bus low to read a bit. data is guaranteed to be valid within 1 s of this falling edge, and remains valid for 14 s minimum. (15 s total from falling edge on 1-wire bus.) note 8: an additional reset or comm unication sequence cannot begin until the reset high time has expired. note 9: the reset low time (t rstl ) should be restricted to a maximum of 960 s, to allow interrupt signaling; otherwise it could mask or conceal interrupt pulses.

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